This application is related to Japanese application No. HEI 11 (1999)-327119 filed on Nov. 17, 1999, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, it relates to a method of manufacturing a nonvolatile semiconductor memory, which is one kind of semiconductor device, particularly utilizing a self-aligned silicidation (SALICIDE) technique and a self-aligned contact (SAC) technique.
2. Description of Related Art
In semiconductor devices, the size reduction of contact holes and the junction of diffusion layers in a shallow region tend to occur due to miniaturization of the devices, which leads to the increase in contact resistance and parasitic resistance. A self-aligned silicide technique has been utilized as means of decreasing the contact resistance and the parasitic resistance. According to the technique, a metal film is deposited on a silicon region where electrical conduction is required, the metal is annealed to form sillcide and then unreacted metal is removed so that only the silicide remains. A common self-aligned silicide technique according to the prior art will be explained hereinafter.
FIGS. 15(a) to 15(c) show an example of the self-aligned silicide technique applied to the production of a MOS transistor.
As shown in FIG. 15(a), a gate electrode 14 is formed with the intervention of a gate insulating film 13 on an active region defined between device isolation regions 12 formed in a silicon substrate 1. On both sides of the gate electrode 14, high concentration diffusion layers are formed in the silicon substrate 1 to serve as a source 15a and a drain 16a, respectively. Further, sidewall spacers 28 are formed on the sidewalls of the gate electrode 14. On the silicon substrate 1 including the thus constructed gate electrode, a metal film (cobalt, titanium or the like) is deposited and thermally treated for silicidation. Then, unreacted metal film is removed to complete metal silicide layers 18, 19 and 20 on the gate electrode 14, the source 15a and the drain 16a, respectively. According to this method, the bottom of the metal silicide layer 18 is located higher than the top of the sidewall spacers 28.
In another aspect, it is getting difficult to arrange a great distance between the contact and the gate electrode as the semiconductor devices are further miniaturized. Accordingly, a self-aligned contact technique has been proposed, in which a film different in material from the interlayer insulating film is formed on the top and the sidewalls"" of the gate electrode to prevent the gate electrode from coming into contact with or getting closer to the contact. A number of variations of the technique have been known, among which a method utilizing a silicon nitride film as an etch stop layer is studied in detail.
For the self-aligned contact formation according to the method, after the metal silicide film 18 is formed, a silicon nitride film 21 is deposited on the silicon substrate 1 to cover the gate electrode 14. Then an interlayer insulating film 22 of a silicon oxide film is deposited thereon (FIG. 15(b)). Photolithography method and etching method are then performed to open contact holes 23 and 24 in the interlayer insulating film 22. This etching process is performed to selectively remove the interlayer insulating film 22 until the top of the silicon nitride film 21, which serves as the etch stop film, is exposed, and then to selectively remove the silicon nitride film 21 until the top of the metal silicide film is exposed (FIG. 15(c)).
In the above, the self-aligned silicide technique and the self-aligned contact technique are applied to form a common MOS transistor. FIGS. 16(a) to 16(c) show sectional views cut along a bit line of a nonvolatile semiconductor memory for illustrating manufacturing processes according to the same techniques. FIGS. 16(a) to 16(c) correspond to FIGS. 15(a) to 15(c). In FIGS. 16(a) to 16(c), reference numeral 2 denotes a gate insulating film, 3 a floating gate silicon film, 4 an insulating film of an ONO film formed between the gates and 5 a control gate silicon film.
However, in the conventional self-aligned contact technique, if the contact hole is mal-aligned and formed above a sidewall spacer arranged on a sidewall of the gate electrode, the distance between a contact part to be formed in the contact hole and the gate electrode (in particular a silicide portion) is reduced and as a result, dielectric strength therebetween tends to decrease.
To solve such a problem, Japanese Unexamined Patent Publication No. HEI 11 (1999)-17181 discloses a method utilizing both the self-aligned silicide (SALICIDE) technique and the self-aligned contact (SAC) technique, and at the same time inhibiting the decrease of the dielectric strength between the gate electrode and the contact part even if the contact holes are mal-aligned. This method will be explained with reference to FIGS. 17(a) to 17(e).
FIG. 17(a) shows a sectional view of a MOS transistor, in which reference numeral 9 denotes a thermal oxidization film and 30 an offset oxide film. A resist layer 29 is applied to the entire surface of the MOS transistor and etched back until the top surface of the offset oxide film 30 is exposed. Then, the offset oxide film 30 on the gate electrode 14 is selectively removed while leaving the unremoved resist layer 29 (FIG. 17(b)).
The gate electrode 14, the source 15a and the drain 16a are simultaneously subjected to silicidation (FIG. 17(c)). Then, a silicon nitride film 21 and an interlayer insulating film 22 are deposited over the entire surface (FIG. 17(d)), followed by the formation of contact holes 23 and 24 (FIG. 17(e)).
In the thus constructed MOS transistor, even if the contact holes 23 and 24 are mal-aligned, electrical conduction due to the swelling of the silicide can be inhibited by the offset oxide film 30 and the sidewall spacers 28 formed on the sidewalls thereof. Further, the reduction of the dielectric strength between the gate electrode 14 and the contact part can be prevented because of the presence of the silicon nitride film 21 on the gate electrode 14.
In the above, the method is utilized to form the MOS transistor, but it can also be applied to form a nonvolatile semiconductor memory by forming the floating gate silicon film 3, the insulating film 4 between the gates, the control gate silicon film 5 and the nitride film in this order on the gate insulating film 13 so that the control gate silicon film 5 serves as the gate electrode 14 and the nitride film serves as the offset oxide film 30.
However, as the memory cells are further miniaturized, the contact hole may be mal-aligned and situated above the gate electrode, which induces short circuit between the contact part in the diffusion region and the gate electrode.
Further, additional steps, i.e., the formation and etch back of the resist layer 29 and the removal of the offset oxide film must be performed.
Moreover, a masking step is also added to remove the insulating film for the silicidation of the surface of the control gate silicon film.
An object of the present invention is to inhibit the reduction of the dielectric strength between the gate electrode and the contact part in the diffusion region, without any additional step to remove the insulating film on the gate electrode separately.
Thus, according to the present invention, provided is a method of manufacturing a semiconductor device comprising the steps of:
(a) depositing a gate insulating film, a floating gate silicon film, an insulating film between gates, and a control gate silicon film in this order on a silicon substrate and forming thereon a third insulating film;
(b) etching said films until the silicon substrate is exposed to form a gate electrode and to open regions for a source and a drain;
(c) removing the third insulating film while leaving it on one end or both ends of the gate electrode in the direction of channel length so that the control gate silicon film is partially exposed;
(d) forming sidewall spacers on sidewalls of the gate electrode and the third insulating film remaining on the gate electrode;
(e) depositing a refractory metal film over the entire surface; and
(f) performing a thermal treatment for simultaneous silicidation of the refractory metal film with the exposed control gate silicon film and the silicon substrate to form a metal silicide layer on each of the exposed control gate silicon film and the silicon substrate.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.